As I was writing the tiler for my little graphics core, I kept having to do some fiddly state management for streaming a block of bytes from RAM to do rendering.
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As I was writing the tiler for my little graphics core, I kept having to do some fiddly state management for streaming a block of bytes from RAM to do rendering. So, factored that out into a little DMA engine that can stream a chunk of memory, forwards or back, with optional restriction to a window of addrs where the read wraps around as needed. With that, both pixel rendering and tile map rendering get simplified to "calculate a DMA request and do a little extra work on the resulting bytes".
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It's really nice not having a particular deadline, it means as I figure out the shape of a piece of gateware, I can go back and factor pieces out, clean up, make things easier to follow, ... A very pleasing cycle of messy prototype to cleaned up code.
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M. J. Frombergerreplied to Dave Anderson last edited by
@danderson And realistically, given the complexity of what you are doing, it's not as if you are taking an unreasonable amount of time to do it even if you DID have a schedule for it.
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Dave Andersonreplied to M. J. Fromberger last edited by
@creachadair I suspect if I were a trained HDL person working more traditionally, I'd be further along by now just because I'd be snapping together more premade parts from libraries or wizards, and would already have trained my brain to know the good design patterns rather than having to figure them out as I go. So, definitely going slower than it's possible to, but I'm not unhappy about my velocity vs. the results I'm getting