A view of the placed and routed design in nextpnr.
-
A view of the placed and routed design in nextpnr. Blue are the embedded block RAMs, whose position is fixed. The orange box contains all the design's logic (UART, data converters, memory controller). The rest is a huge grid of wires transporting signals from the memory controller to the RAMs and back. The vertical lines spanning the entire design is the reset signal, which comes in from the bottom of the image. There's also clocks in there somewhere, but not sure if that net is displayed here.
-
I guess in this view it's quite easy to predict where the long pole is going to be Memory access has to get from that orange block of logic all the way to the relevant RAM primitive and then back. Some RAMs are nice and close, but if the bits you need are at the end of those two long rows, well, settle in for the journey.
-
@danderson time for you to invent multi-tiered caches or something?
-
@jann nah the VRAM is built as a tree of modules, if I insert some buffer flip-flops between them that should give nextpnr enough flexibility to shorten the signal paths intelligently, at the cost of memory access taking more clock cycles (but with a faster enough clock, worth it)