Hmm, okay, my synthesis of this RAM might not yet be _quite_ right. I'm pretty sure a 9-bit write address isn't supposed to expand into a 270-bit address by the time it reaches the RAM...
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Hmm, okay, my synthesis of this RAM might not yet be _quite_ right. I'm pretty sure a 9-bit write address isn't supposed to expand into a 270-bit address by the time it reaches the RAM...
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Hmm, though at the same time, yosys's optimization passes have done something quite cursed here it seems. The 9-bit input address is getting concatenated to 0x9, then thrown through a bunch of multiply-accumulates and ALUs to compute... something. I assume that transformation is correct and just optimizing some of the terrible address math that has to take place, but that still fails to explain how I'm ending up with an address that's 27x wider than what I started with...
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Strangest of all, this is only happening in the write path? The read path just grabs the slightly widened address out and plugs that into the read port, so I end up with a memory that's got a 15-bit read port address, and 270 bits on the write port... It's _possible_ that this is a correct translation of my intent, but it sure looks wacky... Let's see what RTLIL says...
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@danderson That's some serious error correction bits... *ducks*
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@jmax the amount of math getting synthesized seems out of proportion for the amount of math in my source text... So either this is doing something very clever, or... ???