@lofty huh, hmm, okay I suppose.
-
@lofty huh, hmm, okay I suppose. This gateware is a bit odd in that there's not any CPU to speak of so the "direct" in DMA is a bit nonsensical because there's no indirect memory access anywhere... But yeah I guess by wikipedia's definitions this is a maybe slightly oddly shaped first-party DMA engine operating in cycle-stealing mode (or really whatever behavior the bus arbitrator implicitly imposes on the port)
-
@lofty Okay, well, sounds like I need to look for a term that's in the family of DMA engines to describe this particular one.
Hmm, maybe this is a burst mode adapter? It's converting a transactional interface into a burst interface, albeit not necessarily one that locks the bus for the entire burst... But something like that?
-
@lofty From sibling thread: as I started implementing I realized I needed a bunch of fancier features like reading forwards or backwards, wrapping at certain addresses and the like. And as soon as it was doing more than just N consecutive reads, my brain immediately recognized this as a DMA engine without argument. Silly brain. Thank you for the wisdom!