she rlwinm on my immediate til i branch unconditionally [incredibly loud instruction-TLB miss]

[atax1a@infosec.exchange]

she rlwinm on my immediate til i branch unconditionally [incredibly loud instruction-TLB miss]

[arrjay@tacobelllabs.net]

@atax1a hit by the memory bus

[cr1901@mastodon.social]

@atax1a *Looks up rlwinm semantics*

Wow, that's a mouthful :o... what an interesting insn...

[atax1a@infosec.exchange]

@cr1901 raymond chen calls it the swiss-army knife of ppc

[erincandescent@erincandescent.net]

@atax1a @cr1901 The AArch64 [SU]?BFM instructions are similarly swiss army knife and very pleasing for their flexibility (and how many friendly mnemonics are mapped to them)

[taral@mastodon.social]

@erincandescent @atax1a @cr1901 Wait, did rlwinm come back? I thought it was dead!

[taral@mastodon.social]

@erincandescent @atax1a @cr1901 Sorry for jumping in, but I *just* was researching why later CPUs didn't include anything so flexible, and it basically came down to "too much happening in one instruction, simpler instructions enable faster clocks".

[atax1a@infosec.exchange]

@taral @erincandescent @cr1901 32-bit (and 26-bit) ARM has always had the barrel shifter, UBFM seems like a natural extension