Today's interest: just how does a modern PC motherboard implement soft ATX power control?
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Today's interest: just how does a modern PC motherboard implement soft ATX power control? Presumably the main CPU isn't running all the time, although parts of the motherboard are powered. Is there a separate little always-on SOC that implements the logic? Something more clever?
The information is probably somewhere on the Internet but my search luck on this is 'lol no', probably since I don't know the right technical terms to look for.
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Haelwenn /элвэн/ :triskell:replied to Chris Siebenmann last edited by@cks As in suspend-on-ram / S3 deep-sleep?
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Chris Siebenmannreplied to Haelwenn /элвэн/ :triskell: last edited by
@lanodan I was thinking more things like how the BIOS setting for 'when power is restored, stay off/turn on/return to last state' is actually implemented. But apparently that is probably entwined with the S3/etc sleep logic, which I guess I shouldn't be surprised by.
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Haelwenn /элвэн/ :triskell:replied to Chris Siebenmann last edited by@cks deep-sleep logic at least somewhat makes sense to me, I think it's mostly turning of the peripherals and a special mode on the CPU similar to turning cores off.
While power back to last state is weird to me given how I conceptualize ATX power as "pushing the power button pulls ATX pin 16 (green) low and then mobo keeps low while on".
Kind of makes me wish someone like Ben Eater would explain it. ^^ -
@cks I thought this function was provided by the BMC.
Maybe you’re looking for something more specific / precise.
I’ll watch to learn more.
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Erin 💽✨replied to Haelwenn /элвэн/ :triskell: last edited by
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@drscriptt @cks This might be a useful starting place, giving an example of connections between a BMC and the rest of a server-grade system. https://www.issi.com/US/newsletter/Issue86_June_2021/ISSI_BMC-Engangement.pdf
At first, I was assuming that at least part of the PCH or equivalent would need to be powered-up for remote management, to allow for PCIe communication between the BMC and the management NIC, but maybe the RGMII connection eliminates that need? Maybe that's only for machines with a dedicated management NIC? Anyway, I've ended-up with more questions than answers after trying to dive-in to this topic.
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@0x0ddc0ffee @drscriptt Per https://tacobelllabs.net/@arrjay/113105614521811597 desktops handle this in the PCH. I suspect the core handling is there even on servers with a BMC and the BMC talks to the PCH over the 1x PCI lane shown in the diagram. I think BMC management via shared NICs is lower level (and weirder) than the PCH, but really you want dedicated and thus separately powered management NICs.
(Powering the BMC portion of the board must also be fun times. Hopefully it's very low power.)
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Chris Siebenmannreplied to Chris Siebenmann last edited by
@0x0ddc0ffee @drscriptt In theory I guess you could have the (soft) power switch wired to the BMC as basically a GPIO pin and then the BMC controlling the 'power switch' wired to the PCH or wherever it would go, but that seems more indirect and failure prone than just giving the BMC direct PCI access to the PCH to control chipset/platform level power management.
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In theory I guess you could have the (soft) power switch wired to the BMC as basically a GPIO pin and then the BMC controlling the 'power switch' wired to the PCH or wherever it would go
On the platforms I've developed BMC firmware for that's pretty much exactly how it's arranged. Yes, it's more moving parts between the physical button and actually powering on the host, though often mitigated somewhat by a "GPIO pass-through" feature of popular BMC SoCs (Aspeed parts, at least), wherein you can configure the GPIO controller to basically just bridge two pins together in hardware so there's no software in between and it acts like a direct connection, which can be useful for times when the software that usually manages those GPIOs isn't able to do so for whatever reason (like during the BMC's boot sequence).
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@zev @cks @0x0ddc0ffee @drscriptt for modern servers (where modern is basically.. everything since around when AMD released EPYC or so?) there is no PCH. The BMC handles basically all legacy IO functions.
Power on is triggered by the BMC tickling the pin on the ATX connector and then the CPU starts reading the BIOS from the BIOS ROM over either LPC or eSPI