lol what the fuck, did a bunch of stuff to eliminate that long path, rerun synthesis all triumphant like... Fmax dropped from 149MHz to 129MHz??
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lol what the fuck, did a bunch of stuff to eliminate that long path, rerun synthesis all triumphant like... Fmax dropped from 149MHz to 129MHz??
I hate these stupid computers, this makes no sense, I removed the slow bit, why has it gotten slower
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Okay so no idea why the slowness only appeared when I removed that other combinatorial path, but it makes sense, I think. My transceiver input is a BypassFIFO, which saves a cycle when the FIFO is empty and both writer and reader fire on the same cycle, but it does so by creating a combinatorial pathway through the FIFO... which is long, and therefore slow.
Replacing it with a PipelineFIFO fixes that, but I'm still only back up to 145MHz, and the strobe module is still the slowpoke.
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Staring at the output, I think I'm at some fundamental limit of this FPGA: the critical path is read a number from a register, add a constant to it, pass the result through a selector mux, and (assuming it passed the mux) write back to the same register.
The long path is from bit 0 of that register to bit 7, representing the carry chain as it ripples through the adder.
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@danderson too much fan-out somewhere, slowing signal rise/fall because the current is spread too thin? That's all I got from this distance.
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And indeed, the timing report says that the logic elements contribute 2.7ns of delay, whereas the routing to ripple and propagate is 4.2ns. That routing delay is really the killer, it pushes the total delay on this path to 6.9ns (nice), just a hair over the 6.66ns (the timing of the beast) required to hit 150MHz.
So... I need to make the additions narrower, or come up with the strobe signal in some alternative way that doesn't involve a ripple addition.
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@dr2chase Yeah, see rest of thread, you beat me to it by a little bit. Removing one long path de-registerized another path and so introduced a long path. Fixing that took me back to my strobe module, but this time the timing analysis is simpler: "you asked to have an 8-bit add and a selector mux between two registers. Fastest I can do that is 145MHz, if you want to go faster, get rid of that carry propagation between the bit additions."
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Hrm, and yet, setting up a simpler test case with just an adder, I can pass timing at 340MHz.
So... I must be reading the timing analysis wrong, something else is going on that's generating more delay somewhere in here...