@0x0ddc0ffee @drscriptt In theory I guess you could have the (soft) power switch wired to the BMC as basically a GPIO pin and then the BMC controlling the 'power switch' wired to the PCH or wherever it would go, but that seems more indirect and failure prone than just giving the BMC direct PCI access to the PCH to control chipset/platform level power management.
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Today's interest: just how does a modern PC motherboard implement soft ATX power control? -
Today's interest: just how does a modern PC motherboard implement soft ATX power control?@0x0ddc0ffee @drscriptt Per https://tacobelllabs.net/@arrjay/113105614521811597 desktops handle this in the PCH. I suspect the core handling is there even on servers with a BMC and the BMC talks to the PCH over the 1x PCI lane shown in the diagram. I think BMC management via shared NICs is lower level (and weirder) than the PCH, but really you want dedicated and thus separately powered management NICs.
(Powering the BMC portion of the board must also be fun times. Hopefully it's very low power.)
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Today's interest: just how does a modern PC motherboard implement soft ATX power control?@lanodan I was thinking more things like how the BIOS setting for 'when power is restored, stay off/turn on/return to last state' is actually implemented. But apparently that is probably entwined with the S3/etc sleep logic, which I guess I shouldn't be surprised by.
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Today's interest: just how does a modern PC motherboard implement soft ATX power control?Today's interest: just how does a modern PC motherboard implement soft ATX power control? Presumably the main CPU isn't running all the time, although parts of the motherboard are powered. Is there a separate little always-on SOC that implements the logic? Something more clever?
The information is probably somewhere on the Internet but my search luck on this is 'lol no', probably since I don't know the right technical terms to look for.